In the past, we had discussed two transmit, one receive antenna Alamouti Space Time Block Coding (STBC) scheme. In this post, lets us discuss the impact of having two antennas at the receiver. For the discussion, we will assume that the channel is a flat fading Rayleigh multipath channel and the modulation is BPSK.
Author: Krishna Sankar
IQ imbalance in transmitter
Typical communication systems use I-Q modulation and we had discussed the need for I-Q modulation in the past. In this post, let us understand I-Q imbalance and its effect on transmit signal.
Approximate Vector Magnitude Computation
In this post, let us discuss a simple implementation friendly scheme for computing the absolute value of a complex number . The technique called
(alpha Max + beta Min) algorithm is discussed in Chapter 13.2 of Understanding Digital Signal Processing, Richard Lyons
The magnitude of a complex number is
.
The simplified computation of the absolute value is
where
.
Derivation of BPSK BER in Rayleigh channel
This is a guest post by Jose Antonio Urigüen who is an Electrical and Electronic Engineer currently studying an MSc in Communications and Signal Processing at Imperial College in London. This guest post has been created due to his own curiosity when reviewing some concepts of BER for BPSK in Rayleigh channnel published in the dsplog.com
From the post on BER for BPSK in Rayleigh channnel, it was shown that, in the presence of channel , the effective bit energy to noise ratio is
.
Continue reading “Derivation of BPSK BER in Rayleigh channel”
Soft Input Viterbi decoder
In two previous posts, we have discussed Convolutional Coding and the associated hard decision Viterbi decoding. In this post lets extent Viterbi decoding algorithm to soft input decision scheme. The modulation used is BPSK and the channel is assumed to be AWGN alone.
Migration to Who’s Who theme
After a gap of around 7 months, we decided to migrate to a new template (recall, last time we changed was in May 2008). The template which we decided to use is designed by Elegant Themes. They have a wide array of themes and I chose to use the Who’s Who theme.
Viterbi decoder
Coding is a technique where redundancy is added to original bit sequence to increase the reliability of the communication. Lets discuss a simple binary convolutional coding scheme at the transmitter and the associated Viterbi (maximum likelihood) decoding scheme at the receiver.
Update: For some reason, the blog is unable to display the article which discuss both Convolutional coding and Viterbi decoding. As a work around, the article was broken upto into two posts.
This post descrbes the Viterbi decoding algorithm for a simple Binary Convolutional Code with rate 1/2, constraint length and having generator polynomial
. For more details on the Binary convolutional code, please refer to the post – Convolutional code
Convolutional code
Coding is a technique where redundancy is added to original bit sequence to increase the reliability of the communication. In this article, lets discuss a simple binary convolutional coding scheme at the transmitter and the associated Viterbi (maximum likelihood) decoding scheme at the receiver.
Update: For some reason, the blog is unable to display the article which discuss both Convolutional coding and Viterbi decoding. As a work around, the article was broken upto into two posts. This post descrbes a simple Binary Convolutional Coding scheme. For details on the Viterbi decoding algorithm, please refer to the post – Viterbi decoder.
Chapter 8, Table 8.2-1 of Digital Communications by John Proakis lists the various rate 1/2 convolutional coding schemes. The simplest among them has constraint length with generator polynomial
. There are three parameters which define the convolotional code:
Books
Happy holidays! 🙂
Wishing every one merry Christmas and a great year 2009 and beyond.
I will list down some of the books which I have on my desk. They help me with the math and simulations
Digital Communication: Third Edition, by John R. Barry, Edward A. Lee, David G. Messerschmitt
MIMO with ML equalization
We have discussed quite a few receiver structures for a 2×2 MIMO channel namely,
(a) Zero Forcing (ZF) equalization
(b) Minimum Mean Square Error (MMSE) equalization
(c) Zero Forcing equalization with Successive Interference Cancellation (ZF-SIC)
(d) ZF-SIC with optimal ordering and
(e) MIMO with MMSE SIC and optimal ordering
From the above receiver structures, we saw that MMSE equalisation with optimally ordered Successive Interference Cancellation gave the best performance. In this post, we will discuss another receiver structure called Maximum Likelihood (ML) decoding which gives us an even better performance. We will assume that the channel is a flat fading Rayleigh multipath channel and the modulation is BPSK.
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MIMO with MMSE SIC and optimal ordering
This post attempts to build further on the MIMO equalization schemes which we have discussed –
(a) Minimum Mean Square Error (MMSE) equalization,
(b) Zero Forcing equalization with Successive Interference Cancellation (ZF-SIC) and
(c) ZF-SIC with optimal ordering.
We have learned that successive interference cancellation with optimal ordering improves the performance with Zero Forcing equalization. In this post, we extend the concept of successive interference cancellation to the MMSE equalization and simulate the performance. We will assume that the channel is a flat fading Rayleigh multipath channel and the modulation is BPSK.
MIMO with ZF SIC and optimal ordering
In previous posts, we had discussed equalization of a 2×2 MIMO channel with Zero Forcing (ZF) equalization and later, Zero Forcing equalization with successive interference cancellation (ZF-SIC). In this post, we will explore a variant of ZF-SIC called Zero Forcing Successive Interference Cancellation with optimal ordering. We will assume that the channel is a flat fading Rayleigh multipath channel and the modulation is BPSK.
Linear to log conversion
In signal processing blocks like power estimation used in digital communication, it may be required to represent the estimate in log scale. This post explains a simple linear to log conversion scheme proposed in the DSP Guru column on DSP Trick: Quick-and-Dirty Logarithms. The scheme makes implementation of a linear to log conversion simple and small in a digital hardware like FPGA.