Skip to content

DSP LOG

Signal Processing

Random Articles
  • About
    • Articles
  • Advertise
  • Blog
  • Home
  • Search
  • Home
  • jitter

jitter

  • Analog

ADC SNR with clock jitter and quantization noise

Krishna Sankar13 years ago13 years ago11 mins

My friend and colleague Mr. Vineet Srivastava pointed me to a nice article on  clock jitter – Clock Jitter Effects on Sampling : A tutorial – by Carlos Azeredo-Leme, IEEE Circuits and Systems Magazine, Third Quarter 2011. In this post, let us discuss the total Signal to Noise Ratio at the output of an analog to…

Read More

Tag

16-PSK 16-QAM 802.11a 2012 Alamouti AWGN BPSK Capacity Communication conference Digital Diversity ECE electromagnetics eye diagram first order FSK GATE Gray IISc interpolation machine_learning Math MIMO ML MMSE modulator noise Nyquist OFDM PAM pdf phase phase_noise PSK pulse shaping QAM raised cosine Rayleigh SIC STBC TETRA transmitter Viterbi ZF

Categories

Archives

Comment

  • Krishna Sankar on Download free e-book on error probability in AWGN
  • rohini on Download free e-book on error probability in AWGN
  • yousif on Alamouti STBC with 2 receive antenna
  • Krishna Sankar on MIMO with Zero Forcing equalizer
  • Krishna Sankar on Bit Error Rate (BER) for BPSK modulation
  • Krishna Sankar on MIMO with MMSE equalizer
  • Krishna Sankar on BER for BPSK in ISI channel with Zero Forcing equalization

Recent Posts

  • Gradients for linear regression
  • Migrated to Amazon EC2 instance (from shared hosting)
  • GATE-2012 ECE Q28 (electromagnetics)
  • Image Rejection Ratio (IMRR) with transmit IQ gain/phase imbalance
  • GATE-2012 ECE Q15 (communication)

DSP

  • ANALOG & DSP
  • Complex to Real
  • DSP DesignLine
  • DSP Guide
  • DSPRelated
  • Octave
  • Octave-Forge
  • Online Scientific Calculator (from EEWeb.com)

FPGA

  • FPGA Central

General

  • Amit Agarwal – Digital Inspiration
  • Enchanting Kerala